8255 Programmable Peripheral Interface(PPI)-
The Intel 8255 (or i8255) programmable peripheral interface (PPI) chip was developed and manufactured by Intel in the first half of the 1970s for the Intel 8080 microprocessor and is a member of the MCS-85 Family of chips. The i8255 was also used with the Intel 8085 and Intel 8086[1] and their descendants and found wide applicability in digital processing systems. It was later cloned by other manufacturers.
The Intel 8255A is a general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
Similar chips-
The i8255 has a similar function to the MOS Technology 6522 (Versatile Interface Adapter) and the MOS Technology CIA (Complex Interface Adapter) all developed for the 6502 family. Other such chips are the 2655 Programmable Peripheral Interface from the Signetics 2650 family of microprocessors, the Motorola 6820 PIA (Peripheral Interface Adapter) from the Motorola 6800 family, the Western Design Center WDC 65C21, an enhanced 6520, and many others.Application Of 8255 Programmable Peripheral Interface-
The 8255 is widely used in many microcomputer/microcontroller systems and home computers such as the SV-328 and all MSX models. The 8255 is used in the original IBM-PC, PC/XT, PC/jr and clones, along with numerous homebuilt computers such as the N8VEM. The 8255 is also directly compatible with the Z-80, as well as many Intel processors.8255 Programmable Peripheral Interface (PPI)
Data Bus BufferThis three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status informa-tion are also transferred through the data bus buffer.
Read/Write and Control Logic-
The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 8255.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.
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| The 8255 PPI chip Architecture |
PIN CONFIGRATION OF 8255:-
D0 - D7 These are the data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines.
CS (Chip Select Input). If this line is a logical 0, the microprocessor can read and write to the 8255.
RD (Read Input) Whenever this input line is a logical 0 and the RD input is a logical 0, the 8255 data outputs are enabled onto the system data bus.
WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical 0, data is written to the 8255 from the system data bus
A0 - A1 (Address Inputs) The logical combination of these two input lines determines which internal register of the 8255 data is written to or read from.
RESET The 8255 is placed into its reset state if this input line is a logical 1. All peripheral ports are set to the input mode.
PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports. They can be connected to peripheral devices. The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines of an external device. These lines are labeled PA0-PA7, PB0-PB7, and PC0-PC7. The groups of the signals are divided into three different I/O ports labeled port A (PA), port B (PB), and port C (PC).
Control Word Register-
Before going to discuss the detailed description about the usage of the 8255 in the MZ-700, you should see the bit definitions of the 8255 control word register (port $E003 of the MZ-700).If bit 7 of the control word is a logical 1 then the 8255 will be configured.
If bit 7 of the control word is a logical 0 then each bit of the port C can be set or reset.
Bit definitions of the 8255 control register to modify single bits of port C.
Examples:
If you want to set/reset bit 0 of port C then set D3 to D1 to 000.
Bit 1 of port C will be set/reset if you code 001 to D3 to D1.
Bit 6 of port C is set/reset if D3 to D1 is 110.
